The present invention relates to a method and/or architecture for a split transaction bus generally and, more particularly, to a simple mechanism for guaranteeing in-order read data returns on a split transaction bus.
A master device, such as a central processing unit, on a split transaction capable bus may request read data items from multiple slave devices on the bus. Because the slave devices may have different read latencies, the read data items can return to the master device out-of-order (i.e. the read data items return in a different order than the read requests). If the master device can have multiple read requests outstanding, there must be some method for handling out-of-order read returns. Current approaches require that the master device keeps track of all outstanding read requests, have some way of identifying which read goes with which request, and some mechanism for reordering the read data items.
The current approaches require a great deal of complexity to deal with a situation that does not occur often in many systems. Most reads are to a single slave device, such as a dynamic random access memory controller, with occasional reads from input/output (I/O) devices. High performance I/O can be handled by a separate direct memory access (DMA) controller or separate channels of a single DMA controller that moves data between a single I/O device and memory.
The present invention concerns a circuit that may be used with a split transaction bus. The circuit generally comprises a register logic and a compare logic. The register logic may be configured to (i) present a first identification signal associated with a first slave device to perform a first transaction and (ii) store a second identification signal associated with a second slave device in place of the first identification signal responsive to a ready signal presented by the second slave device. The compare logic may be configured to (i) compare the second identification signal with the first identification signal and (ii) present a back off signal responsive to the compare.
The objects, features and advantages of the present invention include providing a method and/or architecture for a circuit that (i) may guarantee that read data items return in-order and/or (ii) may cause both the master device and the slave device to ignore transactions that may cause read data items to return out-or-order on a split transaction bus.